Current demands for high density and performance associated with ultra large scale integration require design rules of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. As device scaling plunges into the deep sub-micron ranges, it becomes increasingly difficult to maintain performance and reliability.
In the manufacture of conventional complementary metal oxide semiconductor (CMOS) devices, referring to FIG. 1A, isolation regions 110, called field oxide regions, are formed in a semiconductor substrate 100 of silicon dioxide by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI). A conductive gate 130, such as polysilicon, is also formed on substrate 100, with a gate oxide layer 120 in between. Dielectric spacers 140 are formed on sidewalls of the gate 130, and source/drain regions 150 are formed on either side of gate 130 by implantation of impurities.
As gate lengths are reduced below 0.5 .mu.m, refractory metal silicide layers, such as titanium silicide, are typically formed over source/drain regions 150 and gate 130 to reduce the sheet resistance of these components, thereby improving device performance. Referring to FIG. 1B, a titanium layer 160 is deposited, as by sputtering, over the entire substrate 100 as well as field oxide 110, gate 130 and spacers 140. A low temperature rapid thermal anneal (RTA) reaction creates a first-phase titanium silicide (TiSi.sub.2 --C49) on the exposed silicon of gate 130 and source/drain regions 150. The unreacted titanium over field oxide 110 and spacers 140 is then removed, and a high temperature RTA reaction changes the first-phase titanium silicide into a low-resistance second-phase titanium silicide 170 (TiSi.sub.2 --C54), as shown in FIG. 1C. Since the titanium silicide does not form on field oxide 110 or spacers 140, it is self-aligned to the gate 130 and source/drain regions 150. Hence, the titanium silicide formed in this process is known as "titanium salicide" (self-aligned silicide).
Titanium salicide is effective in decreasing sheet resistance if the gate width is greater than about 0.251 .mu.m. At a gate width of about 0.25 .mu.m the titanium silicide sheet resistance rises dramatically due to narrow-line effects; that is, the low-resistance silicide TiSi.sub.2 --C54 does not completely form because first-phase TiSi.sub.2 --C49 grains are very large (about 0.5 .mu.m), and hence there are fewer nucleation sites on the gate to nucleate the low resistance silicide TiSi.sub.2 --C54 during the high temperature RTA.
To maintain low sheet resistance as gate widths are decreased in scale below about 0.25 .mu.m, cobalt is typically used instead of titanium in silicide formation. Cobalt silicide does not display the undesirable narrow-line effects of titanium silicide because the conversion from its first-phase (CoSi) to its low-resistance second-phase (CoSi.sub.2) is a diffusion reaction, rather than the nucleation and growth reaction of titanium silicide, and therefore the relationship of grain size to gate size is not a limiting factor.
However, the cobalt salicide process has a drawback in that cobalt silicide is more likely than titanium silicide to cause source and drain junction leakage, which can result in unacceptably high power dissipation as well as functional failure. This problem becomes especially critical as gate widths are scaled below 0.25 .mu.m, and source and drain junctions are typically made shallower to prevent transistor short-channel effects. Since shallow junctions are more susceptible to junction leakage than deep junctions, cobalt silicide related junction leakage effectively limits CMOS device scaling.
Referring to FIG. 2, a cause of this junction leakage is the unevenness of the interface between the cobalt silicide 210 and the silicon source/drain regions 220, which results in an insufficient distance between portions of the bottom of the cobalt silicide 210 and source/drain junctions 220a. When a junction 220a is biased, a depletion region (i.e., an area depleted of free carriers) is formed which extends on either side of the junction 220a. Since the distance the depletion region spreads from the junction 220a is inversely proportional to the doping of the region, and source/drain region 220 is more heavily doped than substrate 200, the depletion region spreads mainly into substrate 200. Nevertheless, if cobalt silicide 210 extends into the depletion region, leakage can occur as carriers are swept across this highly charged region.
Junction leakage also occurs due to consumption of substrate silicon during silicide formation. For example, when cobalt silicide is formed to a given thickness, an amount of substrate silicon almost as great as the thickness of the silicide is consumed. As junctions become shallower with device scaling, consumption of substrate silicon during silicidation results in an insufficient distance between portions of the bottom of the cobalt silicide 210 and source/drain junctions 220a and, hence, junction leakage. Junction integrity can be maintained by providing a large enough distance between junction 220a and the interface of silicide 210 and source/drain region 220; i.e., by reducing the thickness of cobalt silicide 210. However, reducing its thickness increases the sheet resistance of cobalt silicide 210, thus reducing its effectiveness. Alternatively, junction leakage can be avoided by forming deeper source/drain regions. However, this is not desirable as it leads to reduced device performance.
There exists a need for a method of manufacturing a semiconductor device with ultra-shallow source/drain junctions and a low-resistance refractory metal silicide layer over its source/drain regions which does not cause junction leakage.